The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for forming gate structures of vertical transistors.
Semiconductor devices are typically formed using active regions of a wafer. In an integrated circuit (IC) having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. A conventional geometry for MOSFETs is known as a planar device geometry in which the various parts of the MOSFET device are laid down as planes or layers.
One type of MOSFET is a non-planar FET known generally as a vertical FET (VFET). VFETs employ semiconductor fins and surround-gates that can be contacted outside the active region, resulting in increased device density and increased performance over lateral devices. In VFETs, the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration a major substrate surface is horizontal and a vertical fin extends upward from the substrate surface. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the fin sidewalls.